1. Field of the Invention
The present invention generally relates to a polishing method for planarizing a substrate and, more particularly, to a polishing method for planarizing a substrate which is applied to fabrication of a multi-layer thin film substrate.
The multi-layer thin film substrate is formed by stacking a plurality of layers on a substrate base. A polishing process is performed each time a single layer is formed so that each layer is formed with a high degree of precision. In order to improve productivity of such a multi-layer thin film substrate, it is desired to reduce the process time of a polishing process which takes a relatively long time as compared to that of other processes.
2. Description of the Related Art
When an attempt is made to provide a wiring layer to have a multi-layered structure, thickness is varied between an area where a via or a wiring is formed and an area where such a via or a wiring is not provided. This makes it difficult to provide a multi-layered wiring layer. Accordingly, a wiring layer can be formed in a three-layered structure at the maximum. If the number of layers is increased, a yield or production rate of the multi-layer thin film substrate is considerably decreased. In order to achieve a multi-layered structure having more layers, a method is used in which surface planarization is performed after each layer is formed. Such planarization is accomplished by a polishing referred to as chemical-mechanical polishing (CMP).
However, in order to increase the number of layers or improve the yield rate, polishing by CMP alone is not sufficient, and a further planarization technique is needed. Such a planarization technique is disclosed in "CHEMICAL MECHANICAL POLISHING (CMP) OF COPPER/POLYIMIDE WITH POLISH STOP FOR MICROELECTRONIC INTEGRATION" for the Proceedings of the technical program for the Pan Pacific Microelectronics Symposium, Honolulu, Hi., Feb. 6-8, 1996. In this technique, a photoresist layer is formed on an upper surface of a ceramic substrate base on which a first-layer wiring pattern and pads are formed. An aperture is formed in the photoresist layer at a position corresponding to each of the pads. Then, a copper interconnecting post is formed within each aperture by using a CVD method or a plating method. Thereafter, the photoresist layer is removed, and a dielectric (polyimide) layer is formed. After that, a hard mask layer (stop layer) of tungsten is formed on the dielectric layer. The thus formed structure is polished by CMP using a slurry having a low polishing capability when used on tungsten. According to this method, a fairly good planar layer can be provided. The slurry having a PH value of 3 is used in this method so as to decrease the polishing capability when used on tungsten so that the tungsten layer serves as a stop layer. Additionally, silica (SiO.sub.2), which is suitable for selectively polishing high points, is added to the slurry. The polishing is performed by a single stage process.
However, in order to selectively form the mask layer at a level to stop the polishing, non-planar areas must be masked, resulting in a decrease of productivity. Accordingly, such decrease of the productivity is prevented by forming the mask layer on the entire surface including high points and selectively polishing the high points by using CMP. In order to polish the hard tungsten in a short time, the polishing capability must be increased in a chemical manner by increasing the PH value of the slurry to an alkaline level, or a polishing powder having a high polishing speed must be added to the slurry. However, such a slurry removes even the tungsten layer which is required to serve as a stop layer, and the stop layer may be completely removed before the copper studs and the polyimide layer are planarized by polishing. As a result, a surface of the layer which must be planarized cannot be a planer surface. Accordingly, in order for the stop layer to function well, a silica slurry having a PH value of 3 must be used in the conventional method. However, the conventional method has a low capability for polishing the tungsten on the high points. Additionally, since alumina (Al.sub.2 O.sub.3) which can polish copper and polyimide at a high speed is not added to the slurry, a time needed for polishing to achieve a planarized surface is increased, that is, about 90 minutes. This becomes an obstacle to increased productivity of a multi-layer thin film substrate.